DPDFLAG=READ_DEEP_POWER_DOW, SLEEPFLAG=READ_NO_POWER_DOWN_, PM=DEFAULT_THE_PART_IS
Power control register
| PM | Power mode 0 (DEFAULT_THE_PART_IS): Default. The part is in active or sleep mode. 1 (ARM_WFI_WILL_ENTER_D): ARM WFI will enter Deep-sleep mode. 2 (ARM_WFI_WILL_ENTER_P): ARM WFI will enter Power-down mode. 3 (ARM_WFI_WILL_ENTER_D): ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down). |
| NODPD | A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked. |
| RESERVED | Reserved. Do not write ones to this bit. |
| SLEEPFLAG | Sleep mode flag 0 (READ_NO_POWER_DOWN_): Read: No power-down mode entered. LPC11Uxx is in Active mode. Write: No effect. 1 (READ_SLEEPDEEP_SLE): Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. |
| RESERVED | Reserved. Do not write ones to this bit. |
| DPDFLAG | Deep power-down flag 0 (READ_DEEP_POWER_DOW): Read: Deep power-down mode not entered. Write: No effect. 1 (READ_DEEP_POWER_DOW): Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. |
| RESERVED | Reserved. Do not write ones to this bit. |